1. Field of the Invention
The present invention relates to a single electron transistor, and more particularly, to a method for fabricating a single electron transistor in which the size of an electrically formed quantum dot is reduced.
2. Discussion of the Related Art
There has been a tremendous trend in the semiconductor industry over the years to reduce device size. To illustrate this trend, FIG. 1 provides a graph reflecting the trend in the reduction of the numbers of electrons required for device operation according to an experimental scale-down rule of MOSFETs. FIG. 2 provides a graph showing device reliability degradation according to the experimental scale-down rule of MOSFETs of FIG. 1.
Referring to FIG. 1, the present scale-down trend indicates that if the high density device packing of MOSFETs continues, the number of electrons present in a channel will be reduced from approximately 300 in year 2010 to no more than approximately 30 in year 2020. As shown in FIG. 2, if the number of electrons for operating a device is reduced, a ratio of the statistical variation in the number of electrons which falls to the total number of electrons involved in device operation will gradually increase. Thus, a serious influence on device operation reliability will be raised, and a new device structure will be required to precisely control a single electron. To overcome the limitations arising from the high density integration of MOSFETs, a single electron transistor recently was suggested. The single electron transistor can control a single electron and can operate at a very low voltage. However, a single electron transistor requires difficult technology to form a quantum dot between a few nanometers and tens of nanometers at a specific, highly reproducible position for room temperature operation. Particularly, in order to form a single electron switch, a technology is essential to form one or two quantum dots at a desired position in a desired size rather than a technology to form numerous quantum dots at a high concentration. Therefore, lithography techniques are required to form quantum dots with controllability, reproducibility, and reliability. A minimum line width available with present photo-lithography techniques in semiconductor processes is about 0.2 .mu.m (or 200 nanometers). Therefore, to form a pattern with finer line widths, e-beam direct writing is employed; however this causes problems due to proximity effects. Thus, lines and spaces of desired sizes are difficult to obtain.
FIG. 3 is a perspective view of a related art single electron transistor, and FIGS. 4A-4D are sectional views showing the steps of a related art method for fabricating the single electron transistor of FIG. 3. In the fabrication of the single electron transistor of FIG. 3, quantum dots are defined between two tunnel junctions. However, there have been few experimentally operative single electron transistors at room temperature to date because the necessary quantum dot sizes have relied on accidental effects (for example, polysilicon graining or e-beam irregularity). As a result, those technologies are impracticable for fabricating an integrated circuit. Alternatively, the single electron transistor can be formed by lithography to assure reproducibility in forming quantum dots electrically. FIG. 3 illustrates one of the cases suggested in 1994 in Japan.
Referring to FIGS. 3 and 4D, the related art single electron transistor includes an nMOSFET structure having a first insulating film 4 formed on a semiconductor substrate 1 (not shown in FIG. 3), a lower gate 5 with a small width formed on the first gate insulating film 4, and n type source/drain impurity regions 2 and 3 formed in the semiconductor substrate in a longitudinal direction of the lower gate 5. In addition, a second gate insulating film 6 is formed on an entire surface of the substrate having the nMOSFET formed thereon, and a "U" shaped upper gate 7 is formed on the second gate insulating film 6.
A related art method for fabricating a single electron transistor will now be explained with reference to FIGS. 4A-4D.
Referring to FIG. 4A, a first insulating film 4 of silicon oxide is formed on a semiconductor substrate 1 and BF.sub.2 ions are implanted into insulating film 4 to adjust a threshold voltage. As shown in FIG. 4B, a photoresist film 8 is deposited on the first gate insulating film 4 and patterned by exposure and development to define source/drain regions. Then, the patterned photoresist film 8 is used as a mask during implantation of N type impurity ions (P) to form the source/drain impurity regions 2, 3. As shown in FIG. 4C, the photoresist film 8 is removed, and polysilicon is deposited on an entire surface. Then, the polysilicon is selectively removed to leave the polysilicon in a source/drain 2 and 3 direction, thereby forming a lower gate 5. Next, a second gate insulating film 6 of silicon oxide is deposited on an entire surface including the lower gate 5, and polysilicon 7a is deposited on the second gate insulating film 6. As shown in FIG. 4D, resist (not shown in the drawing) is deposited on the polysilicon 7a, and subjected to e-beam direct writing and etching selectively to remove the polysilicon 7a, thereby forming an upper gate 7. Here, the upper gate 7 includes two portions formed on the second gate insulating film 6 between the source/drain impurity regions 2, 3 in a direction perpendicular to the lower gate 5. That is, the upper gate 7 is designed to define a quantum dot in a channel region between the two portions of the upper gate 7. Preferably, the gap between the two portions of the upper gate 7 should be very small. Also, because the two pieces of the upper gate 7 will have identical voltages applied thereto, ends of the two portions are connected to each other to form a "U" shape.
The operation of the related art single electron transistor will now be explained.
Upon application of a positive voltage to the lower gate 5, a narrow channel that conforms to a quantum wire is formed between the source/drain impurity regions 2 and 3. Then, a negative voltage is applied to the upper gate 7. Because the application of the negative voltage to the two portions of the upper gate 7 forms two potential barriers at a center of the narrow channel region under the upper gate 7, an electrical quantum dot is formed in the channel region between the two pieces of the upper gate 7. Next, the quantum dot formed in the channel region between the upper gate 7 controls the single electron tunneling, thereby operating as a single electron transistor.
However, the related art single electron transistor has a number of fabrication problems. FIGS. 5A-5C are SEMs of upper gate patterns formed by the E-beam direct writing in the related art fabrication method for a single electron transistor. For an electrical signal from a single electron tunneling to overcome thermal noise and be a main signal, a charging energy of one electron, q.sup.2 /2C, should be sufficiently larger than a thermal energy, K.sub.B T. Here, q denotes an electron charge, and C denotes a capacitance of the quantum dot. Therefore, the capacitance of the quantum dot for stable room temperature operation must be 1.2.times.10.sup.-17 or less. This value has been experimentally obtained from a period of oscillation of a single electron tunneling current caused by a voltage applied of approximately 13.8 mV to the lower gate. In this instance, the gap between the two pieces of the upper gate was 0.1 .mu.m (which is limited by present photolithography). However, in the process of FIG. 4D, it is impossible to obtain two lines with the gap of 0.1 .mu.m using e-beam direct writing with reproducibility if the process relies on present e-beam lithography because of the proximity effect in which an electron beam cannot propagate with perfect anisotropy.
A result of the experiment is shown in FIGS. 5A-5C. FIG. 5A illustrates a result of an e-beam direct writing for the upper gate with a line width of 0.33 .mu.m and the gap between the two pieces of the upper gate of 0.178 .mu.m. FIG. 5B illustrates a result of an e-beam direct writing for the upper gate with the line width of 0.38 .mu.m and the gap between the two pieces of the upper gate of 0.23 .mu.m. FIG. 5C illustrates a result of an e-beam direct writing for the upper gate with the line width of 0.24 .mu.m and the gap between the two pieces of the upper gate of 0.218.mu.m. As can be recognized from the above results, if both the line width and the gap approach 0.1 .mu.m in formation of the upper gate pattern, an exact upper gate pattern cannot be formed due to the proximity effect. Therefore, the gap between the two pieces of the upper gate, which determines a size of an electrically formed quantum dot, cannot be formed smaller than the limit of the electron beam lithography and cannot be free from cryogenic operation.